This invention relates to a logic circuit formed on a single semiconductor chip together with a custom-circuit in order to detect the defects of an LSI unit (hereinafter simply referred to as the LSI).
It has become possible to manufacture a custom-circuit LSI in an extremely short time of about 2 to 3 months by the use of a gate array. Recently, therefore, the application of the gate array has been rapidly disseminated. The gate array is a semiconductor chip constructed by arranging a large number of logic cells (e.g., 2-input NAND or NOR gates) in a matrix. The logic cells can be interconnected with a dedicated metal pattern to form a custom-circuit logic function on the chip. The general user selects a gate array having a proper number of logic cells in accordance with the scale of a custom-circuit to be integrated, and designs a particular metal pattern. The manufacture produces a gate array in conformity to the metal pattern designed by the user. In this case, the manufacture furnishes a macro cell pattern for the formation of the respective circuit elements, for example, flip-flop, decoders, adders multiplexers, etc. Consequently, a considerable decrease is realized in a period of time required for the development of the LSI as compared with the case where the LSI is produced without using a gate array. A gate array of the same specification can be applied in common to the custom-circuit LSI units of the various types as a base complement. Therefore, the cost of developing a gate array is reduced by that extent. Where, therefore, the custom-circuit LSI is manufactured in a number of amount 2000 to 3000, the gate array offers the advantage of being provided at low cost.
However, the gate array has the drawbacks that a limitation is imposed on the integration of logic cells in order to allow a wider range for their interconnection. Use of the logic cells constituting a gate array unavoidably requires the use of an extensive metal pattern.
In the defect inspection of the LSI, data on its operation speed and logic function are supplied to a custom-circuit involved in the LSI through bonding pads formed along the peripheral edge of the outer surface of the chip. Determination is made of whether the custom-circuit has made a response to the received data, and further in this case measurement is made of the contents of said response. Where the custom-circuit, for example, the CPU involves a plurality of flip-flops, a tremendous amount of data has to be supplied to check the operation of said CPU. Complications in determining various test items and carrying out such tests have hitherto imposed a tremendous load on the user designer.
A level sensitive scan design (LSSD) may be cited as a known device for facilitating the test. The circuit of the LSSD causes plural flip-flops included in the custom-circuit to respectively act as a shift register. However, the LSSD circuit which involves a large number of signal lines and circuit elements is not adapted to be formed on a gate array chip together with the custom-circuit. The reason is that the formation of the LSSD circuit on the gate array chip considerably reduces a region allowed for the provision of the custom-circuit; and the signal lines of the custom-circuit have often to detour around the LSSD circuit, thereby probably decreasing the operation speed of the custom-circuits.